Memory devices such as electrically erasable and programmable read-only memories (EEPROMs) and flash electrically erasable and electrically programmable read-only memories (flash EEPROMs) often include functions of electrical programming and erasing. To perform such functions, these memory devices often include either a stacked-gate structure or a split-gate structure.
One of the shortcomings of the stacked-gate structure is the “over-erasure” of the cell contents during erase operations. When erasing memory content, the erase operation is normally sustained for a slightly prolonged time period to ensure complete removal of the electrons previously injected. However, sometimes such a prolonged erase operation results in the removal of excess electrons. As a result, electron holes may form in the floating gate of the device. In severe cases, the stacked-gate transistor may become a depletion transistor, which conducts even in the absence of a control voltage at the control gate.
Split-gate devices are often used to overcome the memory over-erasure shortcoming of stacked-gate devices. Typically, such a device includes a transistor that includes a control gate and a floating gate. The principal advantage of such a configuration is that the transistor is not affected by the state of the floating gate. Instead, the memory transistor remains in its off state, even if the floating-gate is subject to the phenomenon of over-erasure and therefore is in a conductive state. Accordingly, the transistor can maintain its correct state irrespective of the over-erasure condition.
With the advancement of fabrication processes and materials, semiconductor device geometries have continued to decrease. For example, currently, fabrication facilities are producing devices with geometry sizes (e.g., the smallest component or line that may be created using the process) of less than 90 nm. However, the reduction of geometrical sizes frequently introduces new challenges. For example, size reduction of the devices calls for decreased sizes of flash memory cells. However, significant size reduction of flash memory cells may not be achieved pursuant to previously available methods.
Therefore, it is desired to provide an improved system and method of forming split-gate flash memory structures.